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* Fixed various VS warningsClifford Wolf2014-10-18
* Header changes so it will compile on VSWilliam Speirs2014-10-17
* Wrapped math in int constructorWilliam Speirs2014-10-17
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-16
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-16
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-15
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15
* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-12
* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-12
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
* Disabled vhdl2verilog command for win32 buildsClifford Wolf2014-10-11
* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Another $clog2 bugfixClifford Wolf2014-09-08
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-06
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-06
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-22
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-22
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-21
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-21
* Added AstNode::asInt()Clifford Wolf2014-08-21
* Fixed memory leak in DPI function callsClifford Wolf2014-08-21
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* Added support for global tasks and functionsClifford Wolf2014-08-21
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
* Fixed handling of task outputsClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
* Fixed building verific bindingsClifford Wolf2014-08-12
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-07
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05