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Author
Age
*
gcc-4.6 build fixes
Clifford Wolf
2015-09-01
*
Fixed handling of memory read without address
Clifford Wolf
2015-08-22
*
Small corrections to const2ast warning messages
Clifford Wolf
2015-08-17
*
Check base-n literals only contain valid digits
Florian Zeitz
2015-08-17
*
Warn on literals exceeding the specified bit width
Florian Zeitz
2015-08-17
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
*
Keep gcc from complaining about uninitialized variables
Larry Doolittle
2015-08-14
*
Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
*
Fixed handling of [a-fxz?] in decimal constants
Clifford Wolf
2015-08-11
*
Add -noautowire option to verilog frontend
Marcus Comstedt
2015-08-01
*
Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
*
Fixed nested mem2reg
Clifford Wolf
2015-07-29
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Fixed handling of parameters with reversed range
Clifford Wolf
2015-06-08
*
Fixed signedness of genvar expressions
Clifford Wolf
2015-05-29
*
Improvements in BLIF front-end
Clifford Wolf
2015-05-24
*
bugfix in blif front-end
Clifford Wolf
2015-05-18
*
Improved .latch support in BLIF front-end
Clifford Wolf
2015-05-17
*
Added read_blif command
Clifford Wolf
2015-05-17
*
Generalized blifparse API
Clifford Wolf
2015-05-17
*
abc/blifparse files reorganization
Clifford Wolf
2015-05-17
*
Verific build fixes
Clifford Wolf
2015-05-17
*
Verilog front-end: define `BLACKBOX in -lib mode
Clifford Wolf
2015-04-19
*
Ignore celldefine directive in verilog front-end
Clifford Wolf
2015-03-25
*
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
Clifford Wolf
2015-03-01
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Added deep recursion warning to AST simplify
Clifford Wolf
2015-02-20
*
Parser support for complex delay expressions
Clifford Wolf
2015-02-20
*
YosysJS stuff
Clifford Wolf
2015-02-19
*
Convert floating point cell parameters to strings
Clifford Wolf
2015-02-18
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
*
Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
*
Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf
2015-02-14
*
Added AstNode::simplify() recursion counter
Clifford Wolf
2015-02-13
*
Improved read_verilog support for empty behavioral statements
Clifford Wolf
2015-02-10
*
Ignore explicit assignments to constants in HDL code
Clifford Wolf
2015-02-08
*
Fixed a bug with autowire bit size
Clifford Wolf
2015-02-08
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
*
Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Fixed handling of "input foo; reg [0:0] foo;"
Clifford Wolf
2015-01-15
*
Consolidate "Blocking assignment to memory.." msgs for the same line
Clifford Wolf
2015-01-15
*
Enable bison to be customized
Fabio Utzig
2015-01-08
*
Define YOSYS and SYNTHESIS in preproc
Clifford Wolf
2015-01-02
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
*
Added global yosys_celltypes
Clifford Wolf
2014-12-29
*
dict/pool changes in ast
Clifford Wolf
2014-12-29
*
Changed more code to dict<> and pool<>
Clifford Wolf
2014-12-28
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