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* Fixed build of verific bindingsClifford Wolf2014-07-31
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
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* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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* Removed left over debug codeClifford Wolf2014-07-28
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* Fixed part selects of parametersClifford Wolf2014-07-28
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* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
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* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
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* Fixed width detection for part selectsClifford Wolf2014-07-28
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
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* Added proper Design->addModule interfaceClifford Wolf2014-07-27
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* Fixed verific bindings for new RTLIL apiClifford Wolf2014-07-27
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* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-25
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* Updated verific build/test instructionsClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Various fixes in Verific frontend for new RTLIL APIClifford Wolf2014-07-23
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* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
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* Fixed make rules for ilang parserClifford Wolf2014-07-22
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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
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