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* Implemented read_verilog -deferClifford Wolf2014-02-13
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* Added support for functions returning integerClifford Wolf2014-02-12
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* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-11
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* Improved ilang parser error messagesClifford Wolf2014-02-09
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
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* Added read_verilog -setattrClifford Wolf2014-02-05
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* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-04
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* Added support for blanks after -I and -D in read_verilogClifford Wolf2014-02-02
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* Fixed comment/eol parsing in ilang frontendClifford Wolf2014-02-01
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* Added constant size expression support of sized constantsClifford Wolf2014-02-01
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* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
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* Added read_verilog -icells optionClifford Wolf2014-01-29
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* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-24
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* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
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* Added $assert cellClifford Wolf2014-01-19
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* Added Verilog parser support for assertsClifford Wolf2014-01-19
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* Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-18
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* Added verilog_defaults commandClifford Wolf2014-01-17
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* Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-12
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* Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-03
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* Added correct handling of $memwr priorityClifford Wolf2014-01-03
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* Fixed a stupid access after delete bugClifford Wolf2013-12-29
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* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-27
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* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-27
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
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* Added elsif preproc supportClifford Wolf2013-12-18
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* Added support for macro argumentsClifford Wolf2013-12-18
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* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
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* Added const folding support for $signed and $unsignedClifford Wolf2013-12-05
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* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
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* Fixed generate-for (and disabled double warning for auto-wire)Clifford Wolf2013-12-04
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* Added support for $clog2 system functionClifford Wolf2013-12-04
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* Various improvements in support for generate statementsClifford Wolf2013-12-04
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Added support for local regs in named blocksClifford Wolf2013-12-04
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* Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-28
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* Added "src" attribute to processesClifford Wolf2013-11-28
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
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* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
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* Added support for signed parameters in ilangClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Improved handling of initialized registersClifford Wolf2013-11-23
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-22
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-22
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