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* Various fixes in Verific frontend for new RTLIL APIClifford Wolf2014-07-23
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* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Fixed ilang parsing of process attributesClifford Wolf2014-07-22
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* Fixed make rules for ilang parserClifford Wolf2014-07-22
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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
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* Added "inout" ports support to read_libertyClifford Wolf2014-07-16
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* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-16
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* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-16
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* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
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* Added passing of various options to vhdl2verilogClifford Wolf2014-07-12
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* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
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* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
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* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
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* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
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* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
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* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
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* Improved handling of relational op of real valuesClifford Wolf2014-06-17
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* Improved ternary support for real valuesClifford Wolf2014-06-16
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* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
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* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
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* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
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* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
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* Improved parsing of large integer constantsClifford Wolf2014-06-15
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* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
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* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
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* Fixed relational operators for const real expressionsClifford Wolf2014-06-14
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* Added support for math functionsClifford Wolf2014-06-14
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* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
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* Implemented more real arithmeticClifford Wolf2014-06-14
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* Implemented basic real arithmeticClifford Wolf2014-06-14
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* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
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* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
| | | | allways_ff, always_comb, and always_latch
* Add support for cell arraysClifford Wolf2014-06-07
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* Added support for repeat stmt in const functionsClifford Wolf2014-06-07
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* further improved const function supportClifford Wolf2014-06-07
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* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
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