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path: root/kernel/celltypes.h
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* Squashed commit of the following:Ruben Undheim2016-09-23
* Added read-enable to memory modelClifford Wolf2015-09-25
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-16
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added $assume cell typeClifford Wolf2015-02-26
* Added $meminit cell typeClifford Wolf2015-02-14
* Added $equiv cell typeClifford Wolf2015-01-19
* Added global yosys_celltypesClifford Wolf2014-12-29
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-28
* Added functionality to dff2dffe passClifford Wolf2014-12-08
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-08
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* Added $lcu cell typeClifford Wolf2014-09-08
* Added "$fa" cell typeClifford Wolf2014-09-08
* Added $macc cell typeClifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added eval model for $lut cellsClifford Wolf2014-08-31
* Added $alu cell typeClifford Wolf2014-08-30
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-16
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Added module->portsClifford Wolf2014-08-14
* Refactoring of CellType classClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Added $slice and $concat to CellTypes listClifford Wolf2014-02-07
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added $assert cellClifford Wolf2014-01-19
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Fixed even more ConstEval bugs found using xsthammerClifford Wolf2013-06-14
* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-13
* Added log_assert() apiClifford Wolf2013-05-24
* Added additional functionality and cleanups in sigtools.h and celltypes.hClifford Wolf2013-03-15
* Added #ci and #co selection operatorsClifford Wolf2013-03-14
* Added $sr cell type to celltypes.hClifford Wolf2013-03-14
* Added library support to celltypes class and show passClifford Wolf2013-03-03