| Commit message (Expand) | Author | Age |
* | Added addBufGate module method | Clifford Wolf | 2016-02-02 |
* | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
* | rtlil: speed up SigSpec::sort_and_unify() | Rick Altherr | 2016-01-31 |
* | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
* | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
* | rtlil: rewrite remove2() to avoid copying | Rick Altherr | 2016-01-30 |
* | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 |
* | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 |
* | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 |
* | Fixed driver conflict handling (various cmds) | Clifford Wolf | 2015-10-24 |
* | Fixed handling of driver-driver conflicts in wreduce | Clifford Wolf | 2015-10-24 |
* | Added read-enable to memory model | Clifford Wolf | 2015-09-25 |
* | Cosmetic fix in Module::addLut() | Clifford Wolf | 2015-09-18 |
* | Added $tribuf and $_TBUF_ cell types | Clifford Wolf | 2015-08-16 |
* | Fixed handling of [a-fxz?] in decimal constants | Clifford Wolf | 2015-08-11 |
* | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 |
* | Added design->rename(module, new_name) | Clifford Wolf | 2015-06-30 |
* | Added "rename -top new_name" | Clifford Wolf | 2015-06-17 |
* | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 |
* | Fixed "avail_parameters" handling in module clone/copy | Clifford Wolf | 2015-06-08 |
* | Added $eq/$neq -> $logic_not/$reduce_bool optimization | Clifford Wolf | 2015-04-29 |
* | Improved attributes API and handling of "src" attributes | Clifford Wolf | 2015-04-24 |
* | Avoid parameter values with size 0 ($mem cells) | Clifford Wolf | 2015-04-05 |
* | Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types | Clifford Wolf | 2015-04-05 |
* | Added $assume cell type | Clifford Wolf | 2015-02-26 |
* | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 |
* | Added $meminit cell type | Clifford Wolf | 2015-02-14 |
* | Added SigSpec::has_const() | Clifford Wolf | 2015-02-08 |
* | Added cell->known(), cell->input(portname), cell->output(portname) | Clifford Wolf | 2015-02-07 |
* | Skip blackbox modules in design->selected_modules() | Clifford Wolf | 2015-02-03 |
* | Added "equiv_make -blacklist <file> -encfile <file>" | Clifford Wolf | 2015-01-31 |
* | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 |
* | Progress in equiv_simple | Clifford Wolf | 2015-01-21 |
* | Added equiv_make command | Clifford Wolf | 2015-01-19 |
* | Added $equiv cell type | Clifford Wolf | 2015-01-19 |
* | Optimizing no-op cell->setPort() | Clifford Wolf | 2015-01-17 |
* | Removed SigSpec::extend_xx() api | Clifford Wolf | 2015-01-01 |
* | added hashlib::mkhash_init | Clifford Wolf | 2014-12-30 |
* | Added "yosys -X" | Clifford Wolf | 2014-12-29 |
* | Added mkhash_xorshift() | Clifford Wolf | 2014-12-29 |
* | Added memhasher (yosys -M) | Clifford Wolf | 2014-12-28 |
* | Fixed performance bug in object hashing | Clifford Wolf | 2014-12-28 |
* | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 |
* | More dict/pool related changes | Clifford Wolf | 2014-12-27 |
* | More hashtable finetuning | Clifford Wolf | 2014-12-27 |
* | Replaced std::unordered_set (nodict) with Yosys::pool | Clifford Wolf | 2014-12-26 |
* | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 |
* | Added new_dict (hashmap.h) and re-enabled code coverage counters | Clifford Wolf | 2014-12-26 |
* | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 |