Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Added "eval" pass | Clifford Wolf | 2013-06-19 |
* | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 |
* | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 |
* | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 |
* | Create nice errors when calling RTLIL::Module::derive() of base class | Clifford Wolf | 2013-03-26 |
* | initial import | Clifford Wolf | 2013-01-05 |