path: root/kernel/
Commit message (Expand)AuthorAge
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Added eval -vloghammer_report modeClifford Wolf2013-11-06
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "eval" passClifford Wolf2013-06-19
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Improved opt_share for reduce cellsClifford Wolf2013-03-29
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-26
* initial importClifford Wolf2013-01-05