yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29
*	Added memhasher (yosys -M)	Clifford Wolf	2014-12-28
*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28
*	More dict/pool related changes	Clifford Wolf	2014-12-27
*	More hashtable finetuning	Clifford Wolf	2014-12-27
*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
*	Added new_dict (hashmap.h) and re-enabled code coverage counters	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11
*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08
*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08
*	Added $dffe cell type	Clifford Wolf	2014-12-08
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26
*	Fixed various VS warnings	Clifford Wolf	2014-10-18
*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17
*	Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects	Clifford Wolf	2014-10-16
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19
*	Fixed monitor notifications for removed cell	Clifford Wolf	2014-09-14
*	Added $lcu cell type	Clifford Wolf	2014-09-08
*	Added "$fa" cell type	Clifford Wolf	2014-09-08
*	Added $macc cell type	Clifford Wolf	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Added $alu cell type	Clifford Wolf	2014-08-30
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19
*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Refactoring of CellType class	Clifford Wolf	2014-08-14
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05