| Commit message (Expand) | Author | Age |
* | Various win32 / vs build fixes | Clifford Wolf | 2014-10-17 |
* | Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects | Clifford Wolf | 2014-10-16 |
* | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 |
* | Added $_BUF_ cell type | Clifford Wolf | 2014-10-03 |
* | Initialize RTLIL::Const from std::vector<bool> | Clifford Wolf | 2014-09-19 |
* | Fixed monitor notifications for removed cell | Clifford Wolf | 2014-09-14 |
* | Added $lcu cell type | Clifford Wolf | 2014-09-08 |
* | Added "$fa" cell type | Clifford Wolf | 2014-09-08 |
* | Added $macc cell type | Clifford Wolf | 2014-09-06 |
* | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 |
* | Create a default selection stack in RTLIL::Design::Design() | Clifford Wolf | 2014-09-02 |
* | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::... | Clifford Wolf | 2014-09-01 |
* | Added $lut support in test_cell, techmap, satgen | Clifford Wolf | 2014-08-31 |
* | Added design->scratchpad | Clifford Wolf | 2014-08-30 |
* | Added $alu cell type | Clifford Wolf | 2014-08-30 |
* | Fixed module->addPmux() | Clifford Wolf | 2014-08-30 |
* | Added is_signed argument to SigSpec.as_int() and Const.as_int() | Clifford Wolf | 2014-08-24 |
* | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 |
* | Added emscripten (emcc) support to build system and some build fixes | Clifford Wolf | 2014-08-22 |
* | Added mod->addGate() methods for new gate types | Clifford Wolf | 2014-08-19 |
* | Improved sig.remove2() performance | Clifford Wolf | 2014-08-17 |
* | Added module->uniquify() | Clifford Wolf | 2014-08-16 |
* | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 |
* | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 |
* | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 |
* | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 |
* | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 |
* | Added module->ports | Clifford Wolf | 2014-08-14 |
* | Refactoring of CellType class | Clifford Wolf | 2014-08-14 |
* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 |
* | Added support for truncating of wires to wreduce pass | Clifford Wolf | 2014-08-05 |
* | Bugfix in "techmap -extern" | Clifford Wolf | 2014-08-02 |
* | Removed at() method from RTLIL::IdString | Clifford Wolf | 2014-08-02 |
* | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 |
* | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 |
* | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 |
* | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 |
* | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 |
* | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 |
* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 |
* | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 |
* | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 |
* | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 |
* | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 |
* | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 |
* | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 |
* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 |
* | Added std::initializer_list<> constructor to SigSpec | Clifford Wolf | 2014-07-28 |
* | Added cover() to all SigSpec constructors | Clifford Wolf | 2014-07-28 |
* | Added proper Design->addModule interface | Clifford Wolf | 2014-07-27 |