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rtlil.cc
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Author
Age
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Disabled RTLIL::SigSpec::check() in release builds
Clifford Wolf
2014-07-23
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Fixed release build
Clifford Wolf
2014-07-23
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Added RTLIL::SigSpec::repeat()
Clifford Wolf
2014-07-23
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Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ↵
Clifford Wolf
2014-07-23
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optimized
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Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
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Replaced RTLIL::SigSpec::operator!=() with inline version
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
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Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
Clifford Wolf
2014-07-23
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SigSpec refactoring: More cleanups of old SigSpec use pattern
Clifford Wolf
2014-07-22
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SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
Clifford Wolf
2014-07-22
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Removed RTLIL::SigChunk::compare()
Clifford Wolf
2014-07-22
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SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
Clifford Wolf
2014-07-22
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵
Clifford Wolf
2014-07-22
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created interim RTLIL::SigSpec::chunks_rw()
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ↵
Clifford Wolf
2014-07-22
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added accessor functions
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
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Added module->remove(), module->addWire(), module->addCell(), cell->check()
Clifford Wolf
2014-07-21
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Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
Clifford Wolf
2014-07-20
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Added function-like cell creation helpers
Clifford Wolf
2014-07-18
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Fixed RTLIL::SigSpec::append_bit() for appending constants
Clifford Wolf
2014-07-17
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Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
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Add support for cell arrays
Clifford Wolf
2014-06-07
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Added support for dlatchsr cells
Clifford Wolf
2014-03-31
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Fixed typo in RTLIL::Module::addAdff()
Clifford Wolf
2014-03-17
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Fixed typo in RTLIL::Module::{addSshl,addSshr}
Clifford Wolf
2014-03-15
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Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
Clifford Wolf
2014-03-15
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Progress in Verific bindings
Clifford Wolf
2014-03-14
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Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
Clifford Wolf
2014-03-14
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Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
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Fixed a typo in RTLIL::Module::addReduce...
Clifford Wolf
2014-03-10
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Added RTLIL::Module::add... helper methods
Clifford Wolf
2014-03-10
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Improved checking of internal cell conventions
Clifford Wolf
2014-02-08
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Added $slice and $concat cell types
Clifford Wolf
2014-02-07
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Stronger checking of internal cells
Clifford Wolf
2014-02-07
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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
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Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf
2014-02-02
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Added $assert cell
Clifford Wolf
2014-01-19
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Added RTLIL::SigSpec::optimized() API
Clifford Wolf
2014-01-03
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Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
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Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
Clifford Wolf
2013-12-31
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Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
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Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
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Fixes and improvements in RTLIL::SigSpec::parse
Clifford Wolf
2013-12-07
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Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
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Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
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