yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added module->ports	Clifford Wolf	2014-08-14
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*	Refactoring of CellType class	Clifford Wolf	2014-08-14
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
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*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27
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*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26
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*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26
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*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26
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*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26
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*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26
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*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25
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*	Fixed typo in cover id	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Some improvements in SigSpec packing/unpacking and checking	Clifford Wolf	2014-07-24
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*	Small changes regarding cover() and check() in SigSpec	Clifford Wolf	2014-07-24
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*	Added support for YOSYS_COVER_FILE env variable	Clifford Wolf	2014-07-24
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*	Added cover() calls to RTLIL::SigSpec methods	Clifford Wolf	2014-07-24
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*	Added hashing to RTLIL::SigSpec relational and equal operators	Clifford Wolf	2014-07-23
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