| Commit message (Expand) | Author | Age |
|---|
| * | Small changes regarding cover() and check() in SigSpec | Clifford Wolf | 2014-07-24 |
| * | Added support for YOSYS_COVER_FILE env variable | Clifford Wolf | 2014-07-24 |
| * | Added cover() calls to RTLIL::SigSpec methods | Clifford Wolf | 2014-07-24 |
| * | Added hashing to RTLIL::SigSpec relational and equal operators | Clifford Wolf | 2014-07-23 |
| * | Disabled RTLIL::SigSpec::check() in release builds | Clifford Wolf | 2014-07-23 |
| * | Fixed release build | Clifford Wolf | 2014-07-23 |
| * | Added RTLIL::SigSpec::repeat() | Clifford Wolf | 2014-07-23 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 |
| * | Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ... | Clifford Wolf | 2014-07-23 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 |
| * | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 |
| * | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 |
| * | SigSpec refactoring: More cleanups of old SigSpec use pattern | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form | Clifford Wolf | 2014-07-22 |
| * | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
| * | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 |
| * | Fixed RTLIL::SigSpec::append_bit() for appending constants | Clifford Wolf | 2014-07-17 |
| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 |
| * | Fixed typo in RTLIL::Module::addAdff() | Clifford Wolf | 2014-03-17 |
| * | Fixed typo in RTLIL::Module::{addSshl,addSshr} | Clifford Wolf | 2014-03-15 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 |
| * | Progress in Verific bindings | Clifford Wolf | 2014-03-14 |
| * | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 |
| * | Fixed a typo in RTLIL::Module::addReduce... | Clifford Wolf | 2014-03-10 |
| * | Added RTLIL::Module::add... helper methods | Clifford Wolf | 2014-03-10 |
| * | Improved checking of internal cell conventions | Clifford Wolf | 2014-02-08 |
| * | Added $slice and $concat cell types | Clifford Wolf | 2014-02-07 |
| * | Stronger checking of internal cells | Clifford Wolf | 2014-02-07 |
| * | Added generic RTLIL::SigSpec::parse_sel() with support for selection variables | Clifford Wolf | 2014-02-06 |
| * | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 |
| * | Added RTLIL::SigSpec::to_single_sigbit() | Clifford Wolf | 2014-02-02 |
| * | Added $assert cell | Clifford Wolf | 2014-01-19 |
| * | Added RTLIL::SigSpec::optimized() API | Clifford Wolf | 2014-01-03 |
| * | Added correct handling of $memwr priority | Clifford Wolf | 2014-01-03 |
| * | Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint | Clifford Wolf | 2013-12-31 |
| * | Added $bu0 cell (for easy correct $eq/$ne mapping) | Clifford Wolf | 2013-12-28 |
