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* Fixed monitor notifications for removed cellClifford Wolf2014-09-14
* Added $lcu cell typeClifford Wolf2014-09-08
* Added "$fa" cell typeClifford Wolf2014-09-08
* Added $macc cell typeClifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-02
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Added $alu cell typeClifford Wolf2014-08-30
* Fixed module->addPmux()Clifford Wolf2014-08-30
* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-24
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added mod->addGate() methods for new gate typesClifford Wolf2014-08-19
* Improved sig.remove2() performanceClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Refactoring of CellType classClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-02
* Implemented new reference counting RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
* Packed SigBit::data and SigBit::offset in a unionClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added RTLIL::MonitorClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27