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Commit message (Expand)AuthorAge
* Improved checking of internal cell conventionsClifford Wolf2014-02-08
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Stronger checking of internal cellsClifford Wolf2014-02-07
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Added RTLIL::SigSpec::to_single_sigbit()Clifford Wolf2014-02-02
* Added $assert cellClifford Wolf2014-01-19
* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-03
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added additional checks for A_SIGNED == B_SIGNED for cells with that constraintClifford Wolf2013-12-31
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Fixes and improvements in RTLIL::SigSpec::parseClifford Wolf2013-12-07
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Added eval -vloghammer_report modeClifford Wolf2013-11-06
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "eval" passClifford Wolf2013-06-19
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Improved opt_share for reduce cellsClifford Wolf2013-03-29
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-26
* initial importClifford Wolf2013-01-05