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rtlil.cc
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Author
Age
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
*
Added information on all internal cell types to internal checker
Clifford Wolf
2013-11-11
*
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
*
Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
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Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
*
Changed NEW_WIRE API to return the wire, not the signal
Clifford Wolf
2013-10-18
*
Added RTLIL NEW_WIRE macro
Clifford Wolf
2013-10-18
*
Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
*
Added "eval" pass
Clifford Wolf
2013-06-19
*
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
Clifford Wolf
2013-06-18
*
Added "dump" command (part ilang backend)
Clifford Wolf
2013-06-02
*
Improved opt_share for reduce cells
Clifford Wolf
2013-03-29
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Create nice errors when calling RTLIL::Module::derive() of base class
Clifford Wolf
2013-03-26
*
initial import
Clifford Wolf
2013-01-05