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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added RTLIL::MonitorClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Added some missing "const" in rtlil.hClifford Wolf2014-07-26
* Added RTLIL::Module::connections()Clifford Wolf2014-07-26
* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-26
* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-26
* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-25
* Fixed typo in cover idClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Some improvements in SigSpec packing/unpacking and checkingClifford Wolf2014-07-24
* Small changes regarding cover() and check() in SigSpecClifford Wolf2014-07-24
* Added support for YOSYS_COVER_FILE env variableClifford Wolf2014-07-24
* Added cover() calls to RTLIL::SigSpec methodsClifford Wolf2014-07-24
* Added hashing to RTLIL::SigSpec relational and equal operatorsClifford Wolf2014-07-23
* Disabled RTLIL::SigSpec::check() in release buildsClifford Wolf2014-07-23
* Fixed release buildClifford Wolf2014-07-23
* Added RTLIL::SigSpec::repeat()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Replaced RTLIL::SigSpec::operator!=() with inline versionClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)Clifford Wolf2014-07-23
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
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