| Commit message (Expand) | Author | Age |
|---|
| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 |
| * | Fixed typo in RTLIL::Module::addAdff() | Clifford Wolf | 2014-03-17 |
| * | Fixed typo in RTLIL::Module::{addSshl,addSshr} | Clifford Wolf | 2014-03-15 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 |
| * | Progress in Verific bindings | Clifford Wolf | 2014-03-14 |
| * | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 |
| * | Fixed a typo in RTLIL::Module::addReduce... | Clifford Wolf | 2014-03-10 |
| * | Added RTLIL::Module::add... helper methods | Clifford Wolf | 2014-03-10 |
| * | Improved checking of internal cell conventions | Clifford Wolf | 2014-02-08 |
| * | Added $slice and $concat cell types | Clifford Wolf | 2014-02-07 |
| * | Stronger checking of internal cells | Clifford Wolf | 2014-02-07 |
| * | Added generic RTLIL::SigSpec::parse_sel() with support for selection variables | Clifford Wolf | 2014-02-06 |
| * | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 |
| * | Added RTLIL::SigSpec::to_single_sigbit() | Clifford Wolf | 2014-02-02 |
| * | Added $assert cell | Clifford Wolf | 2014-01-19 |
| * | Added RTLIL::SigSpec::optimized() API | Clifford Wolf | 2014-01-03 |
| * | Added correct handling of $memwr priority | Clifford Wolf | 2014-01-03 |
| * | Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint | Clifford Wolf | 2013-12-31 |
| * | Added $bu0 cell (for easy correct $eq/$ne mapping) | Clifford Wolf | 2013-12-28 |
| * | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 |
| * | Fixes and improvements in RTLIL::SigSpec::parse | Clifford Wolf | 2013-12-07 |
| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 |
| * | Massive performance improvement from refactoring RTLIL::SigSpec::optimize() | Clifford Wolf | 2013-11-22 |
| * | Added SigBit struct and refactored RTLIL::SigSpec::extract | Clifford Wolf | 2013-11-22 |
| * | Added information on all internal cell types to internal checker | Clifford Wolf | 2013-11-11 |
| * | Improved user-friendliness of "sat" and "eval" expression parsing | Clifford Wolf | 2013-11-09 |
| * | Renamed extend_un0() to extend_u0() and use it in genrtlil | Clifford Wolf | 2013-11-07 |
| * | Fixed type of sign extension in opt_const $eq/$ne handling | Clifford Wolf | 2013-11-07 |
| * | Added eval -vloghammer_report mode | Clifford Wolf | 2013-11-06 |
| * | Changed NEW_WIRE API to return the wire, not the signal | Clifford Wolf | 2013-10-18 |
| * | Added RTLIL NEW_WIRE macro | Clifford Wolf | 2013-10-18 |
| * | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 |
| * | Added "eval" pass | Clifford Wolf | 2013-06-19 |
| * | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 |
| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 |
| * | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 |
| * | Create nice errors when calling RTLIL::Module::derive() of base class | Clifford Wolf | 2013-03-26 |
| * | initial import | Clifford Wolf | 2013-01-05 |
