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kernel
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rtlil.h
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...
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
*
Added RTLIL::Const::size()
Clifford Wolf
2014-08-31
*
Typo fixes in cell->*Param() API
Clifford Wolf
2014-08-31
*
Added design->scratchpad
Clifford Wolf
2014-08-30
*
Added is_signed argument to SigSpec.as_int() and Const.as_int()
Clifford Wolf
2014-08-24
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
*
Added mod->addGate() methods for new gate types
Clifford Wolf
2014-08-19
*
Added module->uniquify()
Clifford Wolf
2014-08-16
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
*
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf
2014-08-14
*
Added module->ports
Clifford Wolf
2014-08-14
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
*
Fixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf
2014-08-12
*
Added support for truncating of wires to wreduce pass
Clifford Wolf
2014-08-05
*
Added RTLIL::IdString::in(...)
Clifford Wolf
2014-08-04
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
Limit size of log_signal buffer to 100 elements
Clifford Wolf
2014-08-02
*
Improvements in new RTLIL::IdString implementation
Clifford Wolf
2014-08-02
*
Implemented new reference counting RTLIL::IdString
Clifford Wolf
2014-08-02
*
Fixed memory corruption related to id2cstr()
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Added ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf
2014-08-01
*
Packed SigBit::data and SigBit::offset in a union
Clifford Wolf
2014-08-01
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added RTLIL::Monitor
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
*
Added "kernel/yosys.h" and "kernel/yosys.cc"
Clifford Wolf
2014-07-30
*
Added "techmap -map %{design-name}"
Clifford Wolf
2014-07-29
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added std::initializer_list<> constructor to SigSpec
Clifford Wolf
2014-07-28
*
Added proper Design->addModule interface
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpecConstIterator
Clifford Wolf
2014-07-27
*
Added RTLIL::Module::wire(id) and cell(id) lookup functions
Clifford Wolf
2014-07-27
*
Added RTLIL::Design::modules()
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Added conversion from ObjRange to std::vector and std::set
Clifford Wolf
2014-07-27
*
Added RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf
2014-07-27
*
Using std::move() in SigSpec move constructor
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpec move constructor and move assignment operator
Clifford Wolf
2014-07-27
*
Mostly cosmetic changes to rtlil.h
Clifford Wolf
2014-07-27
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