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path: root/kernel/rtlil.h
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* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Added design->full_selection() helper methodClifford Wolf2013-10-27
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Added techmap -opt modeClifford Wolf2013-08-09
* Some fixes to improve determinismClifford Wolf2013-08-09
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "eval" passClifford Wolf2013-06-19
* Fixed build with clangClifford Wolf2013-06-18
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Improved opt_share for reduce cellsClifford Wolf2013-03-29
* Added design->select() api and use it in extract passClifford Wolf2013-03-03
* Added id2cstr APIClifford Wolf2013-03-01
* Do not unescape identifiers starting with \$Clifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05