yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08
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*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07
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*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31
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*	Synced RTLIL::unescape_id() to log_id() behavior	Clifford Wolf	2015-01-30
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*	Added dict/pool.sort()	Clifford Wolf	2015-01-24
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*	Added equiv_make command	Clifford Wolf	2015-01-19
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*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01
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*	Progress in memory_bram	Clifford Wolf	2014-12-31
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*	IdString optimization	Clifford Wolf	2014-12-31
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*	added hashlib::mkhash_init	Clifford Wolf	2014-12-30
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*	Added "yosys -X"	Clifford Wolf	2014-12-29
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*	Converting "share" to dict<> and pool<> complete	Clifford Wolf	2014-12-29
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*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29
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*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28
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*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28
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*	More dict/pool related changes	Clifford Wolf	2014-12-27
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*	More hashtable finetuning	Clifford Wolf	2014-12-27
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*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26
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*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
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*	Added support for multiple clock domains to "abc" pass	Clifford Wolf	2014-12-21
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*	Fixed build with gcc 4.6	Clifford Wolf	2014-12-16
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*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11
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*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08
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*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08
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*	Improved TopoSort determinism	Clifford Wolf	2014-11-07
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*	Fixed a few VS warnings	Clifford Wolf	2014-10-17
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*	Made iterators extend std::iterator and added == operator	William Speirs	2014-10-15
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*	Added support for "keep" on modules	Clifford Wolf	2014-09-29
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*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01
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*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31
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*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31
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*	Added design->scratchpad	Clifford Wolf	2014-08-30
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*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
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*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19
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*	Added module->uniquify()	Clifford Wolf	2014-08-16
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
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*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
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