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path: root/kernel/rtlil.h
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27
* Added RTLIL::Design::modules()Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Using std::move() in SigSpec move constructorClifford Wolf2014-07-27
* Added RTLIL::SigSpec move constructor and move assignment operatorClifford Wolf2014-07-27
* Mostly cosmetic changes to rtlil.hClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Added some missing "const" in rtlil.hClifford Wolf2014-07-26
* Added RTLIL::Module::connections()Clifford Wolf2014-07-26
* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-26
* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-26
* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Small changes regarding cover() and check() in SigSpecClifford Wolf2014-07-24
* Added hashing to RTLIL::SigSpec relational and equal operatorsClifford Wolf2014-07-23
* Added RTLIL::SigSpec::repeat()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Replaced RTLIL::SigSpec::operator!=() with inline versionClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)Clifford Wolf2014-07-23
* SigSpec refactoring: Added RTLIL::SigSpecIteratorClifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::operator[]Clifford Wolf2014-07-22
* Removed RTLIL::SigChunk::compare()Clifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack apiClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...Clifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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