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path: root/kernel/rtlil.h
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Small changes regarding cover() and check() in SigSpecClifford Wolf2014-07-24
* Added hashing to RTLIL::SigSpec relational and equal operatorsClifford Wolf2014-07-23
* Added RTLIL::SigSpec::repeat()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Replaced RTLIL::SigSpec::operator!=() with inline versionClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)Clifford Wolf2014-07-23
* SigSpec refactoring: Added RTLIL::SigSpecIteratorClifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::operator[]Clifford Wolf2014-07-22
* Removed RTLIL::SigChunk::compare()Clifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack apiClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...Clifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Added module->remove(), module->addWire(), module->addCell(), cell->check()Clifford Wolf2014-07-21
* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-20
* Added SIZE() macroClifford Wolf2014-07-20
* Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>Clifford Wolf2014-07-18
* Added function-like cell creation helpersClifford Wolf2014-07-18
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() APIClifford Wolf2014-03-15
* Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate APIClifford Wolf2014-03-14
* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-10
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
* Added RTLIL::SigSpec::to_single_sigbit()Clifford Wolf2014-02-02
* Added select -assert-none and -assert-anyClifford Wolf2014-01-17
* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-03
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Fixed uninitialized const flags bugClifford Wolf2013-12-07
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09