summaryrefslogtreecommitdiff
path: root/kernel/rtlil.h
Commit message (Expand)AuthorAge
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() APIClifford Wolf2014-03-15
* Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate APIClifford Wolf2014-03-14
* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-10
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
* Added RTLIL::SigSpec::to_single_sigbit()Clifford Wolf2014-02-02
* Added select -assert-none and -assert-anyClifford Wolf2014-01-17
* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-03
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Fixed uninitialized const flags bugClifford Wolf2013-12-07
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Added design->full_selection() helper methodClifford Wolf2013-10-27
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Added techmap -opt modeClifford Wolf2013-08-09
* Some fixes to improve determinismClifford Wolf2013-08-09
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "eval" passClifford Wolf2013-06-19
* Fixed build with clangClifford Wolf2013-06-18
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Improved opt_share for reduce cellsClifford Wolf2013-03-29
* Added design->select() api and use it in extract passClifford Wolf2013-03-03
* Added id2cstr APIClifford Wolf2013-03-01
* Do not unescape identifiers starting with \$Clifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05