yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Bugfix in satgen for cells with wider in- than outputs.	Clifford Wolf	2014-07-21
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*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12
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*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
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*	Added $assert support to satgen	Clifford Wolf	2014-01-19
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*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03
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*	Added SAT undef model for $pmux and $safe_pmux	Clifford Wolf	2014-01-02
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*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02
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*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29
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*	Fixed sat handling of $eqx and $nex with unequal port widths	Clifford Wolf	2013-12-27
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*	Small cleanup in SatGen	Clifford Wolf	2013-12-27
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*	Fixed sat handling of $eqx and $nex cells	Clifford Wolf	2013-12-27
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25
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*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
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*	Implemented same div-by-zero behavior as found in other synthesis tools	Clifford Wolf	2013-08-15
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*	Added sat -ignore_div_by_zero switch	Clifford Wolf	2013-08-15
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*	Added SAT support for $div and $mod cells	Clifford Wolf	2013-08-11
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*	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
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*	Another fix for a bug found using xsthammer	Clifford Wolf	2013-06-12
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*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10
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*	Improvements and fixes in SAT code	Clifford Wolf	2013-06-10
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*	Implemented temporal induction proofs in sat_solve	Clifford Wolf	2013-06-09
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*	Fixed handling of $_XOR_ in SAT generator	Clifford Wolf	2013-06-09
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*	Added sequential solving support to sat_solve	Clifford Wolf	2013-06-09
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*	Added support for shifter cells to SAT generator	Clifford Wolf	2013-06-08
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*	Various improvements in sat_solve pass and SAT generator	Clifford Wolf	2013-06-08
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*	Improved sat generator and sat_solve pass	Clifford Wolf	2013-06-07
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*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07