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Author
Age
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Using $pos models for $bu0
Clifford Wolf
2014-09-03
*
Fixes in $alu SAT- and eval-models
Clifford Wolf
2014-09-03
*
Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf
2014-09-02
*
Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf
2014-09-02
*
Added ConstEval model for $alu cells
Clifford Wolf
2014-09-01
*
Added SAT model for $alu cells
Clifford Wolf
2014-09-01
*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
*
Fixed return size of const_*() eval functions
Clifford Wolf
2014-08-31
*
Added RTLIL::Const::size()
Clifford Wolf
2014-08-31
*
Added eval model for $lut cells
Clifford Wolf
2014-08-31
*
Typo fixes in cell->*Param() API
Clifford Wolf
2014-08-31
*
Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
*
Added design->scratchpad
Clifford Wolf
2014-08-30
*
Added $alu cell type
Clifford Wolf
2014-08-30
*
Fixed module->addPmux()
Clifford Wolf
2014-08-30
*
Added is_signed argument to SigSpec.as_int() and Const.as_int()
Clifford Wolf
2014-08-24
*
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
*
Added "plugin" command
Clifford Wolf
2014-08-22
*
Added mod->addGate() methods for new gate types
Clifford Wolf
2014-08-19
*
Fixed proc_{self,share}_dirname error handling
Clifford Wolf
2014-08-17
*
Improved sig.remove2() performance
Clifford Wolf
2014-08-17
*
Added stackmap<> container
Clifford Wolf
2014-08-17
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
*
Added module->uniquify()
Clifford Wolf
2014-08-16
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
*
Added CellTypes::cell_evaluable()
Clifford Wolf
2014-08-16
*
Added log_spacer()
Clifford Wolf
2014-08-16
*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
*
Added Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf
2014-08-15
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
*
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf
2014-08-14
*
Added module->ports
Clifford Wolf
2014-08-14
*
Refactoring of CellType class
Clifford Wolf
2014-08-14
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
*
Fixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf
2014-08-12
*
Another build fix by americanrouter (via reddit)
Clifford Wolf
2014-08-11
*
Fixed build with gcc-4.6
Clifford Wolf
2014-08-07
*
Added support for truncating of wires to wreduce pass
Clifford Wolf
2014-08-05
*
Added RTLIL::IdString::in(...)
Clifford Wolf
2014-08-04
*
Added query() API to ModIndex
Clifford Wolf
2014-08-03
*
Added ID() macro for static IdStrings
Clifford Wolf
2014-08-03
*
Fixed a va_list corruption in logv_error()
Clifford Wolf
2014-08-02
*
Bugfix in "techmap -extern"
Clifford Wolf
2014-08-02
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