index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
kernel
Commit message (
Expand
)
Author
Age
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Use easyer-to-read unoptimized ceil_log2()
Clifford Wolf
2016-02-15
*
Fixed more visual studio warnings
Clifford Wolf
2016-02-14
*
Fixed some visual studio warnings
Clifford Wolf
2016-02-13
*
Added "int ceil_log2(int)" function
Clifford Wolf
2016-02-13
*
Added addBufGate module method
Clifford Wolf
2016-02-02
*
SigMap performance improvement
Clifford Wolf
2016-02-01
*
hashlib mfp<> performance improvements
Clifford Wolf
2016-02-01
*
Added reserve() method to haslib classes and
Clifford Wolf
2016-01-31
*
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
Rick Altherr
2016-01-31
*
rtlil: speed up SigSpec::sort_and_unify()
Rick Altherr
2016-01-31
*
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
Rick Altherr
2016-01-31
*
rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
Rick Altherr
2016-01-31
*
Meaningless coding style change
Clifford Wolf
2016-01-31
*
rtlil: rewrite remove2() to avoid copying
Rick Altherr
2016-01-30
*
rtlil: duplicate remove2() for std::set<>
Rick Altherr
2016-01-29
*
rtlil: change IdString comparison operators to take references instead of copies
Rick Altherr
2016-01-29
*
Added default values for hashlib at() methods
Clifford Wolf
2015-12-02
*
Re-added SigMap::allbits()
Clifford Wolf
2015-11-30
*
Removed dangling ';' in rtlil.h
Clifford Wolf
2015-11-26
*
Improved SigMap performance
Clifford Wolf
2015-10-28
*
Improvements in new SigMap
Clifford Wolf
2015-10-28
*
Removed old SigMap implementation
Clifford Wolf
2015-10-27
*
Added hashlib::mfp and new SigMap
Clifford Wolf
2015-10-27
*
Major refactoring of equiv_struct
Clifford Wolf
2015-10-25
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
Added "equiv_add -cell"
Clifford Wolf
2015-10-25
*
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
*
Fixed driver conflict handling (various cmds)
Clifford Wolf
2015-10-24
*
equiv_purge bugfix, using SigChunk in Yosys namespace
Clifford Wolf
2015-10-24
*
Fixed handling of driver-driver conflicts in wreduce
Clifford Wolf
2015-10-24
*
Added support for ":" as comment symbol after ;-parsing
Clifford Wolf
2015-10-23
*
Progress on cell help messages
Clifford Wolf
2015-10-17
*
Added first help messages for cell types
Clifford Wolf
2015-10-14
*
Added read-enable to memory model
Clifford Wolf
2015-09-25
*
Cosmetic fix in Module::addLut()
Clifford Wolf
2015-09-18
*
Removed unnecessary cast.
Andrei Errapart
2015-09-01
*
Microsoft Visual C++ fixes in hashlib; template specializations on int32_t an...
Andrei Errapart
2015-09-01
*
Microsoft Visual C++ fix for log.h.
Andrei Errapart
2015-09-01
*
Added SigMap::allbits()
Clifford Wolf
2015-08-31
*
Added $tribuf and $_TBUF_ cell types
Clifford Wolf
2015-08-16
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
*
Fixed hashlib for 64 bit int keys
Clifford Wolf
2015-08-12
*
Fixed handling of [a-fxz?] in decimal constants
Clifford Wolf
2015-08-11
*
Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Added design->rename(module, new_name)
Clifford Wolf
2015-06-30
*
Added "rename -top new_name"
Clifford Wolf
2015-06-17
*
Added "write_smv" skeleton
Clifford Wolf
2015-06-15
[next]