yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
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*	Added design->scratchpad	Clifford Wolf	2014-08-30
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*	Added $alu cell type	Clifford Wolf	2014-08-30
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*	Fixed module->addPmux()	Clifford Wolf	2014-08-30
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*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24
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*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
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*	Added "plugin" command	Clifford Wolf	2014-08-22
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*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19
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*	Fixed proc_{self,share}_dirname error handling	Clifford Wolf	2014-08-17
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*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17
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*	Added stackmap<> container	Clifford Wolf	2014-08-17
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
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*	Added module->uniquify()	Clifford Wolf	2014-08-16
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*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16
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*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16
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*	Added log_spacer()	Clifford Wolf	2014-08-16
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
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*	Added Frontend "+/" filename syntax for files from proc_share_dir	Clifford Wolf	2014-08-15
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
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*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	Refactoring of CellType class	Clifford Wolf	2014-08-14
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12
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*	Another build fix by americanrouter (via reddit)	Clifford Wolf	2014-08-11
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*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
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*	Added query() API to ModIndex	Clifford Wolf	2014-08-03
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*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03
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*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02
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*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Added logfile hash to statistics footer	Clifford Wolf	2014-08-01
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*	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
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