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* Added support for scripts with labelsClifford Wolf2014-07-21
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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* Bugfix in satgen for cells with wider in- than outputs.Clifford Wolf2014-07-21
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* Added module->remove(), module->addWire(), module->addCell(), cell->check()Clifford Wolf2014-07-21
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* Added log_ping()Clifford Wolf2014-07-21
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* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
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* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-20
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* Added SIZE() macroClifford Wolf2014-07-20
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* Added log_cell()Clifford Wolf2014-07-20
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* Fixed log_id() memory corruptionClifford Wolf2014-07-19
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* Added ModWalker helper classClifford Wolf2014-07-19
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* Some "const" cleanups in SigMapClifford Wolf2014-07-19
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* Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>Clifford Wolf2014-07-18
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* Added function-like cell creation helpersClifford Wolf2014-07-18
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* Added log_id() helper functionClifford Wolf2014-07-18
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* Fixed RTLIL::SigSpec::append_bit() for appending constantsClifford Wolf2014-07-17
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* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
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* Use "verilog -sv" to parse .sv filesClifford Wolf2014-07-11
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* Add support for cell arraysClifford Wolf2014-06-07
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* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
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* workaround for OpenBSD 'stdout' implementationClifford Wolf2014-05-03
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* workaround for OpenBSD 'stdin' implementationClifford Wolf2014-05-02
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* Added support for dlatchsr cellsClifford Wolf2014-03-31
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* Fixed typo in RTLIL::Module::addAdff()Clifford Wolf2014-03-17
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* Fixed typo in RTLIL::Module::{addSshl,addSshr}Clifford Wolf2014-03-15
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* Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() APIClifford Wolf2014-03-15
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* Added log_dump() support for generic pointersClifford Wolf2014-03-14
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* Progress in Verific bindingsClifford Wolf2014-03-14
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* Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate APIClifford Wolf2014-03-14
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* Hotfix for kernel/compatibility.hClifford Wolf2014-03-13
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
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* - kernel/register.h, kernel/driver.cc: refactor ↵Siesh1oo2014-03-12
| | | | | | | rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-12
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* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed a typo in RTLIL::Module::addReduce...Clifford Wolf2014-03-10
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* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-10
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* Fixed use of frozen literals in SatGenClifford Wolf2014-03-06
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* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-06
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* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
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* Added support for $bu0 to SatGenClifford Wolf2014-02-26
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* Added support for Minisat::SimpSolver + ezSAT frezze() APIClifford Wolf2014-02-23
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* Fixed small memory leak in Pass::call()Clifford Wolf2014-02-23
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* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
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* Improved checking of internal cell conventionsClifford Wolf2014-02-08
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* Added $slice and $concat to CellTypes listClifford Wolf2014-02-07
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* Added $slice and $concat cell typesClifford Wolf2014-02-07
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* Stronger checking of internal cellsClifford Wolf2014-02-07
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* Added echo commandClifford Wolf2014-02-07
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* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
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