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Author
Age
*
Fixed log_id() memory corruption
Clifford Wolf
2014-07-19
*
Added ModWalker helper class
Clifford Wolf
2014-07-19
*
Some "const" cleanups in SigMap
Clifford Wolf
2014-07-19
*
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
Clifford Wolf
2014-07-18
*
Added function-like cell creation helpers
Clifford Wolf
2014-07-18
*
Added log_id() helper function
Clifford Wolf
2014-07-18
*
Fixed RTLIL::SigSpec::append_bit() for appending constants
Clifford Wolf
2014-07-17
*
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
*
Use "verilog -sv" to parse .sv files
Clifford Wolf
2014-07-11
*
Add support for cell arrays
Clifford Wolf
2014-06-07
*
Improved error message for options after front-end filename arguments
Clifford Wolf
2014-06-04
*
workaround for OpenBSD 'stdout' implementation
Clifford Wolf
2014-05-03
*
workaround for OpenBSD 'stdin' implementation
Clifford Wolf
2014-05-02
*
Added support for dlatchsr cells
Clifford Wolf
2014-03-31
*
Fixed typo in RTLIL::Module::addAdff()
Clifford Wolf
2014-03-17
*
Fixed typo in RTLIL::Module::{addSshl,addSshr}
Clifford Wolf
2014-03-15
*
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
Clifford Wolf
2014-03-15
*
Added log_dump() support for generic pointers
Clifford Wolf
2014-03-14
*
Progress in Verific bindings
Clifford Wolf
2014-03-14
*
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
Clifford Wolf
2014-03-14
*
Hotfix for kernel/compatibility.h
Clifford Wolf
2014-03-13
*
Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
*
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...
Siesh1oo
2014-03-12
*
Added libs/minisat (copy of minisat git master)
Clifford Wolf
2014-03-12
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
*
Fixed a typo in RTLIL::Module::addReduce...
Clifford Wolf
2014-03-10
*
Added RTLIL::Module::add... helper methods
Clifford Wolf
2014-03-10
*
Fixed use of frozen literals in SatGen
Clifford Wolf
2014-03-06
*
Strictly zero-extend unsigned A-inputs of shift operations
Clifford Wolf
2014-03-06
*
Fixed const folding of $bu0 cells
Clifford Wolf
2014-02-27
*
Added support for $bu0 to SatGen
Clifford Wolf
2014-02-26
*
Added support for Minisat::SimpSolver + ezSAT frezze() API
Clifford Wolf
2014-02-23
*
Fixed small memory leak in Pass::call()
Clifford Wolf
2014-02-23
*
Added "design -push" and "design -pop"
Clifford Wolf
2014-02-20
*
Improved checking of internal cell conventions
Clifford Wolf
2014-02-08
*
Added $slice and $concat to CellTypes list
Clifford Wolf
2014-02-07
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
*
Stronger checking of internal cells
Clifford Wolf
2014-02-07
*
Added echo command
Clifford Wolf
2014-02-07
*
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
*
Added support for #-comments in same line as command
Clifford Wolf
2014-02-06
*
Added support for backslash continuation in script files
Clifford Wolf
2014-02-06
*
Fixed bug in sequential sat proofs and improved handling of asserts
Clifford Wolf
2014-02-04
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf
2014-02-02
*
Added yosys -H for command list
Clifford Wolf
2014-01-30
*
Added -h command line option
Clifford Wolf
2014-01-29
*
Added $assert support to satgen
Clifford Wolf
2014-01-19
*
Added $assert cell
Clifford Wolf
2014-01-19
*
Some improvements in log_dump_val_worker() templates
Clifford Wolf
2014-01-17
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