yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25
*	Fixed typo in cover id	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Added cover_list() API	Clifford Wolf	2014-07-24
*	Added "cover" command	Clifford Wolf	2014-07-24
*	Some improvements in SigSpec packing/unpacking and checking	Clifford Wolf	2014-07-24
*	Now using a dedicated ELF section for all coverage counters	Clifford Wolf	2014-07-24
*	Small changes regarding cover() and check() in SigSpec	Clifford Wolf	2014-07-24
*	Added support for YOSYS_COVER_FILE env variable	Clifford Wolf	2014-07-24
*	Added cover() calls to RTLIL::SigSpec methods	Clifford Wolf	2014-07-24
*	Added support for YOSYS_COVER_DIR env variable	Clifford Wolf	2014-07-24
*	Added cover() API	Clifford Wolf	2014-07-24
*	Added hashing to RTLIL::SigSpec relational and equal operators	Clifford Wolf	2014-07-23
*	Disabled RTLIL::SigSpec::check() in release builds	Clifford Wolf	2014-07-23
*	Fixed release build	Clifford Wolf	2014-07-23
*	Added RTLIL::SigSpec::repeat()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
*	Replaced RTLIL::SigSpec::operator!=() with inline version	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23
*	Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)	Clifford Wolf	2014-07-23
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
*	SigSpec refactoring: Added RTLIL::SigSpecIterator	Clifford Wolf	2014-07-22
*	SigSpec refactoring: added RTLIL::SigSpec::operator[]	Clifford Wolf	2014-07-22
*	SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form	Clifford Wolf	2014-07-22
*	Removed RTLIL::SigChunk::compare()	Clifford Wolf	2014-07-22
*	SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added support for scripts with labels	Clifford Wolf	2014-07-21
*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21
*	Bugfix in satgen for cells with wider in- than outputs.	Clifford Wolf	2014-07-21
*	Added module->remove(), module->addWire(), module->addCell(), cell->check()	Clifford Wolf	2014-07-21
*	Added log_ping()	Clifford Wolf	2014-07-21
*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20
*	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	Clifford Wolf	2014-07-20
*	Added SIZE() macro	Clifford Wolf	2014-07-20
*	Added log_cell()	Clifford Wolf	2014-07-20
*	Fixed log_id() memory corruption	Clifford Wolf	2014-07-19
*	Added ModWalker helper class	Clifford Wolf	2014-07-19
*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19
*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18