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* Small cleanup in SatGenClifford Wolf2013-12-27
* Fixed sat handling of $eqx and $nex cellsClifford Wolf2013-12-27
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Added log_dump() APIClifford Wolf2013-12-20
* Added "sat" undef support and "sat -set-init" optionsClifford Wolf2013-12-07
* Fixed uninitialized const flags bugClifford Wolf2013-12-07
* Fixes and improvements in RTLIL::SigSpec::parseClifford Wolf2013-12-07
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added Pass:call_newsel APIClifford Wolf2013-12-02
* Added "history" commandClifford Wolf2013-12-02
* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-29
* Improvements in satgen undef handlingClifford Wolf2013-11-25
* Improvements in satgen undef handlingClifford Wolf2013-11-25
* Started implementing undef handling in satgenClifford Wolf2013-11-25
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Some driver changes/fixesClifford Wolf2013-11-22
* Added more performance measurement infrastructureClifford Wolf2013-11-22
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-17
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-09
* More undef-propagation related fixesClifford Wolf2013-11-08
* Removed debug log from const_pow()Clifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Improved undef handling in == and != for ConstEvalClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Fixed handling of undef values in POS cells in ConstEvalClifford Wolf2013-11-06
* Fixed handling of undef values in MUX select input in ConstEvalClifford Wolf2013-11-06
* Added eval -vloghammer_report modeClifford Wolf2013-11-06
* Fixed sign handling in const eval of sshl and sshrClifford Wolf2013-11-05
* Write yosys version to output filesClifford Wolf2013-11-03
* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-27
* Added API and Makefile rules for share/ filesClifford Wolf2013-10-27
* Added design->full_selection() helper methodClifford Wolf2013-10-27
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18