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* Added -h command line optionClifford Wolf2014-01-29
* Added $assert support to satgenClifford Wolf2014-01-19
* Added $assert cellClifford Wolf2014-01-19
* Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-17
* Added select -assert-none and -assert-anyClifford Wolf2014-01-17
* Fixed SAT and ConstEval undef handling for $pmux and $safe_pmuxClifford Wolf2014-01-03
* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-03
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added SAT undef model for $pmux and $safe_pmuxClifford Wolf2014-01-02
* Major rewrite of "freduce" commandClifford Wolf2014-01-02
* Added additional checks for A_SIGNED == B_SIGNED for cells with that constraintClifford Wolf2013-12-31
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-29
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Fixed sat handling of $eqx and $nex with unequal port widthsClifford Wolf2013-12-27
* Small cleanup in SatGenClifford Wolf2013-12-27
* Fixed sat handling of $eqx and $nex cellsClifford Wolf2013-12-27
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Added log_dump() APIClifford Wolf2013-12-20
* Added "sat" undef support and "sat -set-init" optionsClifford Wolf2013-12-07
* Fixed uninitialized const flags bugClifford Wolf2013-12-07
* Fixes and improvements in RTLIL::SigSpec::parseClifford Wolf2013-12-07
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added Pass:call_newsel APIClifford Wolf2013-12-02
* Added "history" commandClifford Wolf2013-12-02
* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-29
* Improvements in satgen undef handlingClifford Wolf2013-11-25
* Improvements in satgen undef handlingClifford Wolf2013-11-25
* Started implementing undef handling in satgenClifford Wolf2013-11-25
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Some driver changes/fixesClifford Wolf2013-11-22
* Added more performance measurement infrastructureClifford Wolf2013-11-22
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-22
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-17
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-09
* More undef-propagation related fixesClifford Wolf2013-11-08
* Removed debug log from const_pow()Clifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07