yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28
*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Added topological sorting to techmap	Clifford Wolf	2014-07-27
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27
*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27
*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27
*	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27
*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27
*	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27
*	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27
*	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Added support for here documents	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26
*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26
*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26
*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26
*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25
*	Fixed typo in cover id	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Added cover_list() API	Clifford Wolf	2014-07-24
*	Added "cover" command	Clifford Wolf	2014-07-24
*	Some improvements in SigSpec packing/unpacking and checking	Clifford Wolf	2014-07-24
*	Now using a dedicated ELF section for all coverage counters	Clifford Wolf	2014-07-24
*	Small changes regarding cover() and check() in SigSpec	Clifford Wolf	2014-07-24
*	Added support for YOSYS_COVER_FILE env variable	Clifford Wolf	2014-07-24
*	Added cover() calls to RTLIL::SigSpec methods	Clifford Wolf	2014-07-24
*	Added support for YOSYS_COVER_DIR env variable	Clifford Wolf	2014-07-24
*	Added cover() API	Clifford Wolf	2014-07-24