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* Added "yosys -A"Clifford Wolf2014-07-31
* Added "yosys -Q"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Added write_file commandClifford Wolf2014-07-30
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-30
* Added "log_dump_val_worker(char *v)"Clifford Wolf2014-07-30
* Added "kernel/yosys.h" and "kernel/yosys.cc"Clifford Wolf2014-07-30
* Added "test_cell" commandClifford Wolf2014-07-29
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Small improvements in PerformanceTimer APIClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-27
* Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-27
* Added log_cmd_error_expectionClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27
* Added RTLIL::Design::modules()Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Using std::move() in SigSpec move constructorClifford Wolf2014-07-27
* Added RTLIL::SigSpec move constructor and move assignment operatorClifford Wolf2014-07-27
* Mostly cosmetic changes to rtlil.hClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added support for here documentsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Added some missing "const" in rtlil.hClifford Wolf2014-07-26
* Added RTLIL::Module::connections()Clifford Wolf2014-07-26
* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-26
* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-26
* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-25
* Disabled cover() for non-linux buildsClifford Wolf2014-07-25
* Fixed typo in cover idClifford Wolf2014-07-25