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* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-22
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-17
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-09
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-09
* More undef-propagation related fixesClifford Wolf2013-11-08
* Removed debug log from const_pow()Clifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Improved undef handling in == and != for ConstEvalClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Fixed handling of undef values in POS cells in ConstEvalClifford Wolf2013-11-06
* Fixed handling of undef values in MUX select input in ConstEvalClifford Wolf2013-11-06
* Added eval -vloghammer_report modeClifford Wolf2013-11-06
* Fixed sign handling in const eval of sshl and sshrClifford Wolf2013-11-05
* Write yosys version to output filesClifford Wolf2013-11-03
* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-27
* Added API and Makefile rules for share/ filesClifford Wolf2013-10-27
* Added design->full_selection() helper methodClifford Wolf2013-10-27
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added version info to yosys command and added -V optionClifford Wolf2013-08-20
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-15
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-15
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-15
* Added SAT support for $div and $mod cellsClifford Wolf2013-08-11
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-11
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-11
* Added techmap -opt modeClifford Wolf2013-08-09
* Some fixes to improve determinismClifford Wolf2013-08-09
* Fixed SigPool::del() methodClifford Wolf2013-08-06
* Added proper deallocation of history bufferClifford Wolf2013-08-06
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "help -write-web-command-reference-manual"Clifford Wolf2013-07-26
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Fixed shift ops with large right hand sideClifford Wolf2013-07-09
* Added "eval" passClifford Wolf2013-06-19
* Fixed build with clangClifford Wolf2013-06-18
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Fixed even more ConstEval bugs found using xsthammerClifford Wolf2013-06-14
* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-13