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* Added module->uniquify()Clifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-16
* Added log_spacer()Clifford Wolf2014-08-16
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Refactoring of CellType classClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-12
* Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-11
* Fixed build with gcc-4.6Clifford Wolf2014-08-07
* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
* Added query() API to ModIndexClifford Wolf2014-08-03
* Added ID() macro for static IdStringsClifford Wolf2014-08-03
* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-02
* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-02
* Implemented new reference counting RTLIL::IdStringClifford Wolf2014-08-02
* Fixed memory corruption related to id2cstr()Clifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Added logfile hash to statistics footerClifford Wolf2014-08-01
* Added per-pass cpu usage statisticsClifford Wolf2014-08-01
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
* Packed SigBit::data and SigBit::offset in a unionClifford Wolf2014-08-01
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added "trace" commandClifford Wolf2014-07-31
* Added RTLIL::MonitorClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added "yosys -A"Clifford Wolf2014-07-31
* Added "yosys -Q"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Added write_file commandClifford Wolf2014-07-30
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-30
* Added "log_dump_val_worker(char *v)"Clifford Wolf2014-07-30
* Added "kernel/yosys.h" and "kernel/yosys.cc"Clifford Wolf2014-07-30
* Added "test_cell" commandClifford Wolf2014-07-29
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29