yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03
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*	Added RTLIL::SigSpec::optimized() API	Clifford Wolf	2014-01-03
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
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*	Added SAT undef model for $pmux and $safe_pmux	Clifford Wolf	2014-01-02
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*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02
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*	Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint	Clifford Wolf	2013-12-31
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*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
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*	Fixed sat handling of $eqx and $nex with unequal port widths	Clifford Wolf	2013-12-27
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*	Small cleanup in SatGen	Clifford Wolf	2013-12-27
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*	Fixed sat handling of $eqx and $nex cells	Clifford Wolf	2013-12-27
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Added log_dump() API	Clifford Wolf	2013-12-20
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*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07
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*	Fixed uninitialized const flags bug	Clifford Wolf	2013-12-07
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*	Fixes and improvements in RTLIL::SigSpec::parse	Clifford Wolf	2013-12-07
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Added Pass:call_newsel API	Clifford Wolf	2013-12-02
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*	Added "history" command	Clifford Wolf	2013-12-02
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*	Using RTLIL::id2cstr for prompt printing	Clifford Wolf	2013-11-29
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
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*	Some driver changes/fixes	Clifford Wolf	2013-11-22
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*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22
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*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22
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*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
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*	Added -v<level> option and some minor driver cleanups	Clifford Wolf	2013-11-17
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*	Added information on all internal cell types to internal checker	Clifford Wolf	2013-11-11
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*	Call internal checker more often	Clifford Wolf	2013-11-10
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*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09
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*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09
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*	More undef-propagation related fixes	Clifford Wolf	2013-11-08
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*	Removed debug log from const_pow()	Clifford Wolf	2013-11-08
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07
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*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07
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*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07
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*	Fixed type of sign extension in opt_const $eq/$ne handling	Clifford Wolf	2013-11-07
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*	Improved undef handling in == and != for ConstEval	Clifford Wolf	2013-11-06
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
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*	Fixed handling of undef values in POS cells in ConstEval	Clifford Wolf	2013-11-06
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*	Fixed handling of undef values in MUX select input in ConstEval	Clifford Wolf	2013-11-06
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*	Added eval -vloghammer_report mode	Clifford Wolf	2013-11-06
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