summaryrefslogtreecommitdiff
path: root/kernel
Commit message (Expand)AuthorAge
* Replaced "#ifdef WIN32" with "#ifdef _WIN32"Clifford Wolf2014-10-09
* Added API for generic cell cost calculationsClifford Wolf2014-10-09
* No rusage on win32Clifford Wolf2014-10-09
* satgen import sigbit apiClifford Wolf2014-10-03
* added resource sharing of $macc cellsClifford Wolf2014-10-03
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* Added support for "keep" on modulesClifford Wolf2014-09-29
* namespace YosysClifford Wolf2014-09-27
* Assert on new logic loops in "share" passClifford Wolf2014-09-21
* Initialize RTLIL::Const from std::vector<bool>Clifford Wolf2014-09-19
* Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)Clifford Wolf2014-09-16
* Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-15
* Fixed monitor notifications for removed cellClifford Wolf2014-09-14
* Added "synth" commandClifford Wolf2014-09-14
* Simplified $fa undef modelClifford Wolf2014-09-08
* Added $lcu cell typeClifford Wolf2014-09-08
* Added "$fa" cell typeClifford Wolf2014-09-08
* Added $macc eval modelClifford Wolf2014-09-06
* Added $macc SAT modelClifford Wolf2014-09-06
* Added $macc cell typeClifford Wolf2014-09-06
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Using $pos models for $bu0Clifford Wolf2014-09-03
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-03
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-02
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Added ConstEval model for $alu cellsClifford Wolf2014-09-01
* Added SAT model for $alu cellsClifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Fixed return size of const_*() eval functionsClifford Wolf2014-08-31
* Added RTLIL::Const::size()Clifford Wolf2014-08-31
* Added eval model for $lut cellsClifford Wolf2014-08-31
* Typo fixes in cell->*Param() APIClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Added $alu cell typeClifford Wolf2014-08-30
* Fixed module->addPmux()Clifford Wolf2014-08-30
* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-24
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added "plugin" commandClifford Wolf2014-08-22
* Added mod->addGate() methods for new gate typesClifford Wolf2014-08-19
* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-17
* Improved sig.remove2() performanceClifford Wolf2014-08-17
* Added stackmap<> containerClifford Wolf2014-08-17
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16