| Commit message (Expand) | Author | Age |
... | |
* | Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ... | Clifford Wolf | 2014-07-23 |
* | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 |
* | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 |
* | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 |
* | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 |
* | SigSpec refactoring: More cleanups of old SigSpec use pattern | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: Added RTLIL::SigSpecIterator | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: added RTLIL::SigSpec::operator[] | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form | Clifford Wolf | 2014-07-22 |
* | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Added support for scripts with labels | Clifford Wolf | 2014-07-21 |
* | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 |
* | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
* | Bugfix in satgen for cells with wider in- than outputs. | Clifford Wolf | 2014-07-21 |
* | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 |
* | Added log_ping() | Clifford Wolf | 2014-07-21 |
* | Added call_on_selection() and call_on_module() API | Clifford Wolf | 2014-07-20 |
* | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 |
* | Added SIZE() macro | Clifford Wolf | 2014-07-20 |
* | Added log_cell() | Clifford Wolf | 2014-07-20 |
* | Fixed log_id() memory corruption | Clifford Wolf | 2014-07-19 |
* | Added ModWalker helper class | Clifford Wolf | 2014-07-19 |
* | Some "const" cleanups in SigMap | Clifford Wolf | 2014-07-19 |
* | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 |
* | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 |
* | Added log_id() helper function | Clifford Wolf | 2014-07-18 |
* | Fixed RTLIL::SigSpec::append_bit() for appending constants | Clifford Wolf | 2014-07-17 |
* | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 |
* | Use "verilog -sv" to parse .sv files | Clifford Wolf | 2014-07-11 |
* | Add support for cell arrays | Clifford Wolf | 2014-06-07 |
* | Improved error message for options after front-end filename arguments | Clifford Wolf | 2014-06-04 |
* | workaround for OpenBSD 'stdout' implementation | Clifford Wolf | 2014-05-03 |
* | workaround for OpenBSD 'stdin' implementation | Clifford Wolf | 2014-05-02 |
* | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 |
* | Fixed typo in RTLIL::Module::addAdff() | Clifford Wolf | 2014-03-17 |
* | Fixed typo in RTLIL::Module::{addSshl,addSshr} | Clifford Wolf | 2014-03-15 |
* | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 |
* | Added log_dump() support for generic pointers | Clifford Wolf | 2014-03-14 |
* | Progress in Verific bindings | Clifford Wolf | 2014-03-14 |
* | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 |
* | Hotfix for kernel/compatibility.h | Clifford Wolf | 2014-03-13 |