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Author
Age
*
Added "design -push" and "design -pop"
Clifford Wolf
2014-02-20
*
Improved checking of internal cell conventions
Clifford Wolf
2014-02-08
*
Added $slice and $concat to CellTypes list
Clifford Wolf
2014-02-07
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
*
Stronger checking of internal cells
Clifford Wolf
2014-02-07
*
Added echo command
Clifford Wolf
2014-02-07
*
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
*
Added support for #-comments in same line as command
Clifford Wolf
2014-02-06
*
Added support for backslash continuation in script files
Clifford Wolf
2014-02-06
*
Fixed bug in sequential sat proofs and improved handling of asserts
Clifford Wolf
2014-02-04
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf
2014-02-02
*
Added yosys -H for command list
Clifford Wolf
2014-01-30
*
Added -h command line option
Clifford Wolf
2014-01-29
*
Added $assert support to satgen
Clifford Wolf
2014-01-19
*
Added $assert cell
Clifford Wolf
2014-01-19
*
Some improvements in log_dump_val_worker() templates
Clifford Wolf
2014-01-17
*
Added select -assert-none and -assert-any
Clifford Wolf
2014-01-17
*
Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
Clifford Wolf
2014-01-03
*
Added RTLIL::SigSpec::optimized() API
Clifford Wolf
2014-01-03
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
*
Added SAT undef model for $pmux and $safe_pmux
Clifford Wolf
2014-01-02
*
Major rewrite of "freduce" command
Clifford Wolf
2014-01-02
*
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
Clifford Wolf
2013-12-31
*
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
Clifford Wolf
2013-12-29
*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
*
Fixed sat handling of $eqx and $nex with unequal port widths
Clifford Wolf
2013-12-27
*
Small cleanup in SatGen
Clifford Wolf
2013-12-27
*
Fixed sat handling of $eqx and $nex cells
Clifford Wolf
2013-12-27
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
*
Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
*
Added log_dump() API
Clifford Wolf
2013-12-20
*
Added "sat" undef support and "sat -set-init" options
Clifford Wolf
2013-12-07
*
Fixed uninitialized const flags bug
Clifford Wolf
2013-12-07
*
Fixes and improvements in RTLIL::SigSpec::parse
Clifford Wolf
2013-12-07
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Added Pass:call_newsel API
Clifford Wolf
2013-12-02
*
Added "history" command
Clifford Wolf
2013-12-02
*
Using RTLIL::id2cstr for prompt printing
Clifford Wolf
2013-11-29
*
Improvements in satgen undef handling
Clifford Wolf
2013-11-25
*
Improvements in satgen undef handling
Clifford Wolf
2013-11-25
*
Started implementing undef handling in satgen
Clifford Wolf
2013-11-25
*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
*
Some driver changes/fixes
Clifford Wolf
2013-11-22
*
Added more performance measurement infrastructure
Clifford Wolf
2013-11-22
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
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