summaryrefslogtreecommitdiff
path: root/kernel
Commit message (Expand)AuthorAge
* Added hashing to RTLIL::SigSpec relational and equal operatorsClifford Wolf2014-07-23
* Disabled RTLIL::SigSpec::check() in release buildsClifford Wolf2014-07-23
* Fixed release buildClifford Wolf2014-07-23
* Added RTLIL::SigSpec::repeat()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Replaced RTLIL::SigSpec::operator!=() with inline versionClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)Clifford Wolf2014-07-23
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
* SigSpec refactoring: Added RTLIL::SigSpecIteratorClifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::operator[]Clifford Wolf2014-07-22
* SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked formClifford Wolf2014-07-22
* Removed RTLIL::SigChunk::compare()Clifford Wolf2014-07-22
* SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack apiClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...Clifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added support for scripts with labelsClifford Wolf2014-07-21
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Bugfix in satgen for cells with wider in- than outputs.Clifford Wolf2014-07-21
* Added module->remove(), module->addWire(), module->addCell(), cell->check()Clifford Wolf2014-07-21
* Added log_ping()Clifford Wolf2014-07-21
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-20
* Added SIZE() macroClifford Wolf2014-07-20
* Added log_cell()Clifford Wolf2014-07-20
* Fixed log_id() memory corruptionClifford Wolf2014-07-19
* Added ModWalker helper classClifford Wolf2014-07-19
* Some "const" cleanups in SigMapClifford Wolf2014-07-19
* Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>Clifford Wolf2014-07-18
* Added function-like cell creation helpersClifford Wolf2014-07-18
* Added log_id() helper functionClifford Wolf2014-07-18
* Fixed RTLIL::SigSpec::append_bit() for appending constantsClifford Wolf2014-07-17
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* Use "verilog -sv" to parse .sv filesClifford Wolf2014-07-11
* Add support for cell arraysClifford Wolf2014-06-07
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
* workaround for OpenBSD 'stdout' implementationClifford Wolf2014-05-03
* workaround for OpenBSD 'stdin' implementationClifford Wolf2014-05-02
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Fixed typo in RTLIL::Module::addAdff()Clifford Wolf2014-03-17
* Fixed typo in RTLIL::Module::{addSshl,addSshr}Clifford Wolf2014-03-15