path: root/manual/CHAPTER_CellLib.tex
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Added read-enable to memory modelClifford Wolf2015-09-25
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Added $assume cell typeClifford Wolf2015-02-26
* Added $equiv cell typeClifford Wolf2015-01-19
* Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-08
* Added $lcu cell typeClifford Wolf2014-09-08
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added $alu cell typeClifford Wolf2014-08-30
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-15
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Added $assert cellClifford Wolf2014-01-19
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added new cell types to manualClifford Wolf2013-12-28
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added Yosys ManualClifford Wolf2013-07-20