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path: root/manual/CHAPTER_CellLib.tex
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* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Added $assert cellClifford Wolf2014-01-19
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added new cell types to manualClifford Wolf2013-12-28
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added Yosys ManualClifford Wolf2013-07-20