Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 |
* | Added $slice and $concat cell types | Clifford Wolf | 2014-02-07 |
* | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 |
* | Added $assert cell | Clifford Wolf | 2014-01-19 |
* | Added correct handling of $memwr priority | Clifford Wolf | 2014-01-03 |
* | Added new cell types to manual | Clifford Wolf | 2013-12-28 |
* | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |
* | Added Yosys Manual | Clifford Wolf | 2013-07-20 |