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* appnote 012 fixClifford Wolf2015-04-04
* Appnote 012Clifford Wolf2015-04-04
* Merge branch 'master' of Irfan2015-04-03
| * Added blif reference to appnote 010Clifford Wolf2015-03-22
| * Added $assume cell typeClifford Wolf2015-02-26
| * Fixed creation of command reference in manualClifford Wolf2015-02-09
| * Updated command reference in manualClifford Wolf2015-02-09
| * Various presentation fixesClifford Wolf2015-02-09
| * Added $equiv cell typeClifford Wolf2015-01-19
| * Improvements in CodingReadmeClifford Wolf2014-12-31
| * Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-08
| * manual/presentation.tex: bg option is unknown with beamer 3.3 in beamercolorboxFabien Marteau2014-12-07
| * suppressing semi-colon at the end of dot filesFabien Marteau2014-12-05
| * Added some missing .gitignore in manual/Clifford Wolf2014-12-04
| * Some fixes in stubnets exampleClifford Wolf2014-11-24
| * Some fixes in presentationClifford Wolf2014-11-08
| * Various documentation updatesClifford Wolf2014-11-08
| * Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* | appnote for verilog to btorAhmed Irfan2015-04-03
* Added $lcu cell typeClifford Wolf2014-09-08
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
* Added $alu cell typeClifford Wolf2014-08-30
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Replaced sha1 implementationClifford Wolf2014-08-01
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Fixed manual/CHAPTER_Prog/stubnets.ccClifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-16
* small changes in presentationClifford Wolf2014-07-02
* Tiny fix in presentationClifford Wolf2014-06-29
* Progress in presentationClifford Wolf2014-06-29
* Progress in presentationClifford Wolf2014-06-26
* Progress in presentationClifford Wolf2014-06-22
* fixed typoClifford Wolf2014-06-21
* Progress in presentationClifford Wolf2014-06-21
* Progress in presentationClifford Wolf2014-06-14
* Progress in presentationClifford Wolf2014-05-06
* Typos and grammar fixes through chapter 4.Anthony J. Bentley2014-05-02
* Typos and grammar fixes through chapter 2.Anthony J. Bentley2014-04-11