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path: root/passes/abc/abc.cc
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* More win32/abc fixesClifford Wolf2014-10-12
* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-12
* Using stringf() instead of asprintf() in "abc" passClifford Wolf2014-10-12
* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-12
* Added API for generic cell cost calculationsClifford Wolf2014-10-09
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* namespace YosysClifford Wolf2014-09-27
* Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-19
* Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-19
* Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-18
* Added "abc -fast"Clifford Wolf2014-09-18
* Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Added "abc -D" for setting delay targetClifford Wolf2014-08-14
* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-13
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
* Added abc -keepff optionClifford Wolf2014-02-14
* updated default ABC command stringsClifford Wolf2014-02-13
* Updated ABCClifford Wolf2014-02-13
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
* Updated ABC and some related changesClifford Wolf2014-02-13
* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
* Added support for "keep" attribute to abc passClifford Wolf2014-02-08
* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-07
* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim fa...Clifford Wolf2014-02-06
* Added "retime" to standard ABC recipesClifford Wolf2014-02-06
* Added support for inline commands to abc -scriptClifford Wolf2014-02-04