Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Renamed temp module generated by "abc" pass from "logic" to "netlist" | Clifford Wolf | 2013-11-19 |
* | Fixed abc pass blif parser for constant bits | Clifford Wolf | 2013-11-13 |
* | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 |