yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	namespace Yosys	Clifford Wolf	2014-09-27
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Fixed memory corruption in passes/abc/blifparse.cc	Clifford Wolf	2014-03-11
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*	Fixed use of limited length buffer in ABC blif parser	Clifford Wolf	2013-12-31
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*	Added abc -dff and -clk support	Clifford Wolf	2013-12-31
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*	Always use BLIF as ABC output format	Clifford Wolf	2013-12-31
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*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19
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*	Fixed abc pass blif parser for constant bits	Clifford Wolf	2013-11-13
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*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23