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* Improved ABC clock domain partitioningClifford Wolf2014-12-23
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* Added "abc -markgroups"Clifford Wolf2014-12-23
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* Added support for multiple clock domains to "abc" passClifford Wolf2014-12-21
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* Fixed "abc" pass for clk and enable signals driven by logicClifford Wolf2014-12-21
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* Added DFFE support to "abc" passClifford Wolf2014-12-20
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* Also look for yosys-abc in parent dir on win32Clifford Wolf2014-10-18
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* Header changes so it will compile on VSWilliam Speirs2014-10-17
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* More win32/abc fixesClifford Wolf2014-10-12
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* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-12
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* Using stringf() instead of asprintf() in "abc" passClifford Wolf2014-10-12
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* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-12
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* Added API for generic cell cost calculationsClifford Wolf2014-10-09
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* Added $_BUF_ cell typeClifford Wolf2014-10-03
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* namespace YosysClifford Wolf2014-09-27
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* Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-19
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* Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-19
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* Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-18
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* Added "abc -fast"Clifford Wolf2014-09-18
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* Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Added module->portsClifford Wolf2014-08-14
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* Added "abc -D" for setting delay targetClifford Wolf2014-08-14
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* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-13
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* - kernel/register.h, kernel/driver.cc: refactor ↵Siesh1oo2014-03-12
| | | | | | | rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
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